Please provide a short (approximately 100 word) summary of the following web Content, written in the voice of the original author. If there is anything controversial please highlight the controversy. If there is something surprising, unique, or clever, please highlight that as well. Content: Title: TSMC Details N4X Process for HPC: Extreme Performance at Minimum Leakage Site: At its 2023 Technology Symposium TSMC revealed some additional details about its upcoming  N4X technology  that is designed specifically for high-performance computing (HPC) applications. This node promises to enable ultra-high performance and improve efficiency while maintaining IP compatibility with N4P (4 nm-class) process technology. "N4X truly sets a new benchmark for how we can push extreme performance while minimizing the leakage power penalty," said Yujun Li, TSMC's director of business development who is in charge of the foundry's High Performance Computing Business Division. TSMC's N4X technology belongs to the company's N5 (5 nm-class) family, but it is enhanced in several ways and is optimized for voltages of 1.2V and higher in overdrive mode. To achieve higher performance and efficiency, TSMC's N4X improves transistor design in three three key areas. Firstly, they refined their transistors to boost both processing speed and drive currents. Secondly, the foundry incorporated its new high-density metal-insulator-metal (MiM) capacitors, to provide reliable power under high workloads. Lastly, they modified the the back-end-of-line metal stack to provide more power to the transistors. In particular, N4X adds four new devices on top of the N4P device offerings, including ultra-low-voltage transistors (uLVT) for applications that need to be very efficient, and extremely-low threshold voltage transistors  (eLVT) for applications that need to work at high clocks. For example, N4X uLVT with overdrive offers 21% lower power at the same speed when compared to N4P eLVT, whereas N4X eLVT in OD offers 6% higher speed for critical paths when compared to N4P eLVT. Advertised PPA Improvements of New Process Technologies Data announced during conference calls, events, press briefings and press releases   TSMC N5 vs N7 N5P vs N5 N5HPC vs N5 N4 vs N5 N4P vs N5 N4P vs N4 N4X vs N5 N4X vs N4P N3 vs N5 Power -30% -10% ? lower -22% - ? ? -25-30% Performance +15% +5% +7% higher +11% +6% +15% or more +4% or more +10-15% Logic Area Reduction % (Density) 0.55x -45% (1.8x) - - 0.94x -6% 1.06x 0.94x -6% 1.06x - ? ? 0.58x -42% (1.7x) Volume Manufacturing Q2 2020 2021 Q2 2022 2022 2023 H2 2022 H1 2024? H1 2024? H2 2022 While N4X offers significant performance enhancements compared to N4 and N4P, it continues to use the same SRAM, standard I/O, and other IPs as N4P, which enables chip designers to migrate their designs to N4X easily and cost effectively. Meanwhile, keeping in mind N4X's IP compatibility with N4P, it is logical to expect transistor density of N4X to be more or less in line with that of N4P. Though given the focus of this technology, expect chip designers to use this technology to get extreme performance rather than maximum transistor density and small chip dimensions. TSMC claims that N4X has achieved its SPICE model performance targets, so customers can start using the technology today for their HPC designs that will enter production sometimes next year. For TSMC, N4X is an important technology as HPC designs are expected to be the company's main revenue growth driver in the coming years. The contract maker of chips anticipates HPC to account for 40% of its revenue in 2030 followed by smartphones (30%) and automotive (15%) applications.